Register Bit Masks

Bit field definitions for nRF24L01 registers. More...

Macros
#define	MASK_RX_DR   0b01000000
#define	MASK_TX_DS   0b00100000
#define	MASK_MAX_RT   0b00010000
#define	EN_CRC   0b00001000
#define	CRCO   0b00000100
#define	PWR_UP   0b00000010
#define	PRIM_RX   0b00000001
#define	ENAA_P5   0b00100000
#define	ENAA_P4   0b00010000
#define	ENAA_P3   0b00001000
#define	ENAA_P2   0b00000100
#define	ENAA_P1   0b00000010
#define	ENAA_P0   0b00000001
#define	ERX_P5   0b00100000
#define	ERX_P4   0b00010000
#define	ERX_P3   0b00001000
#define	ERX_P2   0b00000100
#define	ERX_P1   0b00000010
#define	ERX_P0   0b00000001
#define	AW   0b00000011
#define	AW0   0b00000001
#define	AW1   0b00000010
#define	ARD   0b11110000
#define	ARD0   0b00010000
#define	ARD1   0b00100000
#define	ARD2   0b01000000
#define	ARD3   0b10000000
#define	ARC   0b00001111
#define	ARC0   0b00000001
#define	ARC1   0b00000010
#define	ARC2   0b00000100
#define	ARC3   0b00001000
#define	RF_CH0   0b00000001
#define	RF_CH1   0b00000010
#define	RF_CH2   0b00000100
#define	RF_CH3   0b00001000
#define	RF_CH4   0b00010000
#define	RF_CH5   0b00100000
#define	RF_CH6   0b01000000
#define	PLL_LOCK   0b00010000
#define	RF_DR   0b00001000
#define	RF_PWR   0b00000110
#define	RF_PWR0   0b00000010
#define	RF_PWR1   0b00000100
#define	LNA_HCURR   0b00000001
#define	RX_DR   0b01000000
#define	TX_DS   0b00100000
#define	MAX_RT   0b00010000
#define	RX_P_NO   0b00001110
#define	RX_P_NO0   0b00000010
#define	RX_P_NO1   0b00000100
#define	RX_P_NO2   0b00001000
#define	TX_FULL   0b00000001
#define	PLOS_CNT   0b11110000
#define	PLOS_CNT0   0b00010000
#define	PLOS_CNT1   0b00100000
#define	PLOS_CNT2   0b01000000
#define	PLOS_CNT3   0b10000000
#define	ARC_CNT   0b00001111
#define	ARC_CNT0   0b00000001
#define	ARC_CNT1   0b00000010
#define	ARC_CNT2   0b00000100
#define	ARC_CNT3   0b00001000
#define	CD   0b00000001
#define	TX_REUSE   0b01000000
#define	FIFO_FULL   0b00100000
#define	TX_EMPTY   0b00010000
#define	RX_FULL   0b00000010
#define	RX_EMPTY   0b00000001
#define	EN_DPL   0b00000100
#define	EN_ACK_PAY   0b00000010
#define	EN_DYN_ACK   0b00000001

Detailed Description

Bit field definitions for nRF24L01 registers.

Macro Definition Documentation

ARC

#define ARC   0b00001111

Auto Retransmit Count

ARC0

#define ARC0   0b00000001

Auto Retransmit Count bit 0

ARC1

#define ARC1   0b00000010

Auto Retransmit Count bit 1

ARC2

#define ARC2   0b00000100

Auto Retransmit Count bit 2

ARC3

#define ARC3   0b00001000

Auto Retransmit Count bit 3

ARC_CNT

#define ARC_CNT   0b00001111

Count retransmitted packets

ARC_CNT0

#define ARC_CNT0   0b00000001

Auto retransmit count bit 0

ARC_CNT1

#define ARC_CNT1   0b00000010

Auto retransmit count bit 1

ARC_CNT2

#define ARC_CNT2   0b00000100

Auto retransmit count bit 2

ARC_CNT3

#define ARC_CNT3   0b00001000

Auto retransmit count bit 3

ARD

#define ARD   0b11110000

Auto Retransmit Delay

ARD0

#define ARD0   0b00010000

Auto Retransmit Delay bit 0

ARD1

#define ARD1   0b00100000

Auto Retransmit Delay bit 1

ARD2

#define ARD2   0b01000000

Auto Retransmit Delay bit 2

ARD3

#define ARD3   0b10000000

Auto Retransmit Delay bit 3

AW

#define AW   0b00000011

RX/TX Address field width

AW0

#define AW0   0b00000001

Address width bit 0

AW1

#define AW1   0b00000010

Address width bit 1

CD

#define CD   0b00000001

Carrier Detect

CRCO

#define CRCO   0b00000100

CRC encoding scheme

EN_ACK_PAY

#define EN_ACK_PAY   0b00000010

Enable Payload with ACK

EN_CRC

#define EN_CRC   0b00001000

Enable CRC

EN_DPL

#define EN_DPL   0b00000100

Enable Dynamic Payload Length

EN_DYN_ACK

#define EN_DYN_ACK   0b00000001

Enable the W_TX_PAYLOAD_NOACK command

ENAA_P0

#define ENAA_P0   0b00000001

Enable auto acknowledgement data pipe 0

ENAA_P1

#define ENAA_P1   0b00000010

Enable auto acknowledgement data pipe 1

ENAA_P2

#define ENAA_P2   0b00000100

Enable auto acknowledgement data pipe 2

ENAA_P3

#define ENAA_P3   0b00001000

Enable auto acknowledgement data pipe 3

ENAA_P4

#define ENAA_P4   0b00010000

Enable auto acknowledgement data pipe 4

ENAA_P5

#define ENAA_P5   0b00100000

Enable auto acknowledgement data pipe 5

ERX_P0

#define ERX_P0   0b00000001

Enable data pipe 0

ERX_P1

#define ERX_P1   0b00000010

Enable data pipe 1

ERX_P2

#define ERX_P2   0b00000100

Enable data pipe 2

ERX_P3

#define ERX_P3   0b00001000

Enable data pipe 3

ERX_P4

#define ERX_P4   0b00010000

Enable data pipe 4

ERX_P5

#define ERX_P5   0b00100000

Enable data pipe 5

FIFO_FULL

#define FIFO_FULL   0b00100000

TX FIFO full flag

LNA_HCURR

#define LNA_HCURR   0b00000001

Setup LNA gain

MASK_MAX_RT

#define MASK_MAX_RT   0b00010000

Mask interrupt caused by MAX_RT

MASK_RX_DR

#define MASK_RX_DR   0b01000000

Mask interrupt caused by RX_DR

MASK_TX_DS

#define MASK_TX_DS   0b00100000

Mask interrupt caused by TX_DS

MAX_RT

#define MAX_RT   0b00010000

Maximum number of TX retransmits interrupt

PLL_LOCK

#define PLL_LOCK   0b00010000

Force PLL lock signal

PLOS_CNT

#define PLOS_CNT   0b11110000

Count lost packets

PLOS_CNT0

#define PLOS_CNT0   0b00010000

Packet lost count bit 0

PLOS_CNT1

#define PLOS_CNT1   0b00100000

Packet lost count bit 1

PLOS_CNT2

#define PLOS_CNT2   0b01000000

Packet lost count bit 2

PLOS_CNT3

#define PLOS_CNT3   0b10000000

Packet lost count bit 3

PRIM_RX

#define PRIM_RX   0b00000001

Primary RX/TX control

PWR_UP

#define PWR_UP   0b00000010

Power UP

RF_CH0

#define RF_CH0   0b00000001

RF channel frequency bit 0

RF_CH1

#define RF_CH1   0b00000010

RF channel frequency bit 1

RF_CH2

#define RF_CH2   0b00000100

RF channel frequency bit 2

RF_CH3

#define RF_CH3   0b00001000

RF channel frequency bit 3

RF_CH4

#define RF_CH4   0b00010000

RF channel frequency bit 4

RF_CH5

#define RF_CH5   0b00100000

RF channel frequency bit 5

RF_CH6

#define RF_CH6   0b01000000

RF channel frequency bit 6

RF_DR

#define RF_DR   0b00001000

Air Data Rate

RF_PWR

#define RF_PWR   0b00000110

Set RF output power in TX mode

RF_PWR0

#define RF_PWR0   0b00000010

RF output power bit 0

RF_PWR1

#define RF_PWR1   0b00000100

RF output power bit 1

RX_DR

#define RX_DR   0b01000000

Data Ready RX FIFO interrupt

RX_EMPTY

#define RX_EMPTY   0b00000001

RX FIFO empty flag

RX_FULL

#define RX_FULL   0b00000010

RX FIFO full flag

RX_P_NO

#define RX_P_NO   0b00001110

Data pipe number for available payload

RX_P_NO0

#define RX_P_NO0   0b00000010

Data pipe number bit 0

RX_P_NO1

#define RX_P_NO1   0b00000100

Data pipe number bit 1

RX_P_NO2

#define RX_P_NO2   0b00001000

Data pipe number bit 2

TX_DS

#define TX_DS   0b00100000

Data Sent TX FIFO interrupt

TX_EMPTY

#define TX_EMPTY   0b00010000

TX FIFO empty flag

TX_FULL

#define TX_FULL   0b00000001

TX FIFO full flag

TX_REUSE

#define TX_REUSE   0b01000000

Used for a PTX device