nrf24l01.h

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#ifndef NRF24L01_DRIVER_NRF24L01_H
#define NRF24L01_DRIVER_NRF24L01_H
 
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "main.h"
#include "stm32f1xx_hal.h"


#define EMPTY_DATA   (uint8_t *)0xFF
 // End of NRF24L01_MACROS group

 
#define CONFIG        0x00  
#define EN_AA         0x01  
#define EN_RXADDR     0x02  
#define SETUP_AW      0x03  
#define SETUP_RETR    0x04  
#define RF_CH         0x05  
#define RF_SETUP      0x06  
#define STATUS        0x07  
#define OBSERVE_TX    0x08  
#define PRD           0x09  
#define RX_ADDR_P0    0x0A  
#define RX_ADDR_P1    0x0B  
#define RX_ADDR_P2    0x0C  
#define RX_ADDR_P3    0x0D  
#define RX_ADDR_P4    0x0E  
#define RX_ADDR_P5    0x0F  
#define TX_ADDR       0x10  
#define RX_PW_P0      0x11  
#define RX_PW_P1      0x12  
#define RX_PW_P2      0x13  
#define RX_PW_P3      0x14  
#define RX_PW_P4      0x15  
#define RX_PW_P5      0x16  
#define FIFO_STATUS   0x17  
#define DYNPD         0x1C  
#define FEATURE       0x1D  
 // End of NRF24L01_REGISTERS group

 
/* CONFIG Register Bits */
#define MASK_RX_DR    0b01000000  
#define MASK_TX_DS    0b00100000  
#define MASK_MAX_RT   0b00010000  
#define EN_CRC        0b00001000  
#define CRCO          0b00000100  
#define PWR_UP        0b00000010  
#define PRIM_RX       0b00000001  
 
/* EN_AA Register Bits */
#define ENAA_P5       0b00100000  
#define ENAA_P4       0b00010000  
#define ENAA_P3       0b00001000  
#define ENAA_P2       0b00000100  
#define ENAA_P1       0b00000010  
#define ENAA_P0       0b00000001  
 
/* EN_RXADDR Register Bits */
#define ERX_P5        0b00100000  
#define ERX_P4        0b00010000  
#define ERX_P3        0b00001000  
#define ERX_P2        0b00000100  
#define ERX_P1        0b00000010  
#define ERX_P0        0b00000001  
 
/* SETUP_AW Register Bits */
#define AW            0b00000011  
#define AW0           0b00000001  
#define AW1           0b00000010  
 
/* SETUP_RETR Register Bits */
#define ARD           0b11110000  
#define ARD0          0b00010000  
#define ARD1          0b00100000  
#define ARD2          0b01000000  
#define ARD3          0b10000000  
#define ARC           0b00001111  
#define ARC0          0b00000001  
#define ARC1          0b00000010  
#define ARC2          0b00000100  
#define ARC3          0b00001000  
 
/* RF_CH Register Bits */
#define RF_CH0        0b00000001  
#define RF_CH1        0b00000010  
#define RF_CH2        0b00000100  
#define RF_CH3        0b00001000  
#define RF_CH4        0b00010000  
#define RF_CH5        0b00100000  
#define RF_CH6        0b01000000  
 
/* RF_SETUP Register Bits */
#define PLL_LOCK      0b00010000  
#define RF_DR         0b00001000  
#define RF_PWR        0b00000110  
#define RF_PWR0       0b00000010  
#define RF_PWR1       0b00000100  
#define LNA_HCURR     0b00000001  
 
/* STATUS Register Bits */
#define RX_DR         0b01000000  
#define TX_DS         0b00100000  
#define MAX_RT        0b00010000  
#define RX_P_NO       0b00001110  
#define RX_P_NO0      0b00000010  
#define RX_P_NO1      0b00000100  
#define RX_P_NO2      0b00001000  
#define TX_FULL       0b00000001  
 
/* OBSERVE_TX Register Bits */
#define PLOS_CNT      0b11110000  
#define PLOS_CNT0     0b00010000  
#define PLOS_CNT1     0b00100000  
#define PLOS_CNT2     0b01000000  
#define PLOS_CNT3     0b10000000  
#define ARC_CNT       0b00001111  
#define ARC_CNT0      0b00000001  
#define ARC_CNT1      0b00000010  
#define ARC_CNT2      0b00000100  
#define ARC_CNT3      0b00001000  
 
/* CD Register Bits */
#define CD            0b00000001  
 
/* FIFO_STATUS Register Bits */
#define TX_REUSE      0b01000000  
#define FIFO_FULL     0b00100000  
#define TX_EMPTY      0b00010000  
#define RX_FULL       0b00000010  
#define RX_EMPTY      0b00000001  
 
/* FEATURE Register Bits */
#define EN_DPL        0b00000100  
#define EN_ACK_PAY    0b00000010  
#define EN_DYN_ACK    0b00000001  
 // End of NRF24L01_BITMASKS group

 
#define R_REGISTER    0x00  
#define W_REGISTER    0x20  
#define R_RX_PAYLOAD  0x61  
#define W_TX_PAYLOAD  0xA0  
#define FLUSH_TX      0xE1  
#define FLUSH_RX      0xE2  
#define REUSE_TX_PL   0xE3  
#define ACTIVATE      0x50  
#define R_RX_PL_WID   0x60  
#define W_ACK_PAYLOAD 0xA8  
#define W_TX_PAYLOAD_NOACK   0xB0  
#define NOP           0xFF  
 // End of NRF24L01_COMMANDS group


typedef enum {
    nrf24l01_air_data_rate_1mbps = 0,  
    nrf24l01_air_data_rate_2mbps,      
} nrf24l01_air_data_rate;

typedef enum {
    nrf24l01_rf_output_power_minus18dbm = 0,  
    nrf24l01_rf_output_power_minus12dbm,      
    nrf24l01_rf_output_power_minus6dbm,       
    nrf24l01_rf_output_power_0dbm             
} nrf24l01_rf_output_power;

typedef enum{
    nrf24l01_address_width_3bytes = 3,  
    nrf24l01_address_width_4bytes,      
    nrf24l01_address_width_5bytes,      
} nrf24l01_address_width;

typedef enum{
    nrf24l01_auto_retransmit_delay_250us = 0,   
    nrf24l01_auto_retransmit_delay_500us,       
    nrf24l01_auto_retransmit_delay_750us,       
    nrf24l01_auto_retransmit_delay_1000us,      
    nrf24l01_auto_retransmit_delay_1250us,      
    nrf24l01_auto_retransmit_delay_1500us,      
    nrf24l01_auto_retransmit_delay_1750us,      
    nrf24l01_auto_retransmit_delay_2000us,      
    nrf24l01_auto_retransmit_delay_2250us,      
    nrf24l01_auto_retransmit_delay_2500us,      
    nrf24l01_auto_retransmit_delay_2750us,      
    nrf24l01_auto_retransmit_delay_3000us,      
    nrf24l01_auto_retransmit_delay_3250us,      
    nrf24l01_auto_retransmit_delay_3500us,      
    nrf24l01_auto_retransmit_delay_3750us,      
    nrf24l01_auto_retransmit_delay_4000us,      
} nrf24l01_auto_retransmit_delay;

typedef enum{
    nrf24l01_auto_retransmit_count_disable = 0,  
    nrf24l01_auto_retransmit_count_1,             
    nrf24l01_auto_retransmit_count_2,             
    nrf24l01_auto_retransmit_count_3,             
    nrf24l01_auto_retransmit_count_4,             
    nrf24l01_auto_retransmit_count_5,             
    nrf24l01_auto_retransmit_count_6,             
    nrf24l01_auto_retransmit_count_7,             
    nrf24l01_auto_retransmit_count_8,             
    nrf24l01_auto_retransmit_count_9,             
    nrf24l01_auto_retransmit_count_10,            
    nrf24l01_auto_retransmit_count_11,            
    nrf24l01_auto_retransmit_count_12,            
    nrf24l01_auto_retransmit_count_13,            
    nrf24l01_auto_retransmit_count_14,            
    nrf24l01_auto_retransmit_count_15,            
} nrf24l01_auto_retransmit_count;

typedef enum{
    nrf24l01_irq_rx_data_ready = 0,      
    nrf24l01_irq_tx_data_sent,           
    nrf24l01_maximum_retransmitted,      
} nrf24l01_irq;
 // End of NRF24L01_ENUMS group


typedef struct{
    uint8_t nrf24l01_data_pipe_enable;                    
    uint8_t nrf24l01_data_pipe_dyn_payload_length_enable; 
    uint8_t nrf24l01_data_pipe_auto_ack;                  
    uint8_t* nrf24l01_data_pipe_receive_address;          
    uint8_t nrf24l01_data_pipe_payload_width;             
    uint8_t* nrf24l01_data_pipe_payload;                  
} nrf24l01_data_pipe;

typedef struct{
    SPI_HandleTypeDef * spi;                         
    GPIO_TypeDef *irq_port, *ce_port, *csn_port;    
    uint8_t irq_pin, ce_pin, csn_pin;               
    TIM_HandleTypeDef * timer;                       
    uint8_t power_up;                                
    uint8_t primary_rx;                              
    nrf24l01_address_width address_width;            
    nrf24l01_auto_retransmit_delay auto_retransmit_delay; 
    nrf24l01_auto_retransmit_count auto_retransmit_count; 
    uint8_t frequency_channel;                       
    nrf24l01_air_data_rate air_data_rate;           
    nrf24l01_rf_output_power rf_output_power;        
    uint8_t setup_lna_gain;                          
    nrf24l01_data_pipe data_pipe[6];                 
    uint8_t* transmit_address;                       
    uint8_t dynamic_payload_length_enable;           
    uint8_t payload_with_ack_enable;                 
    uint8_t dynamic_ack_enable;                      
} nrf24l01_device;
 // End of NRF24L01_STRUCTS group



nrf24l01_device nrf24l01_get_default_config();

uint8_t nrf24l01_init(nrf24l01_device * device);

void nrf24l01_deinit(nrf24l01_device * device);

uint8_t nrf24l01_init_data_pipe(nrf24l01_device * device, uint8_t pipe_number);
 // End of NRF24L01_INIT group


void nrf24l01_delay(nrf24l01_device * device, uint16_t us);

uint8_t nrf24l01_chip_select(nrf24l01_device * device);

uint8_t nrf24l01_chip_deselect(nrf24l01_device * device);

uint8_t nrf24l01_chip_enable(nrf24l01_device * device);

uint8_t nrf24l01_chip_disable(nrf24l01_device * device);

uint8_t nrf24l01_send_command(nrf24l01_device* device, uint8_t command);
 // End of NRF24L01_LOW_LEVEL group


uint8_t nrf24l01_read_register(nrf24l01_device * device, uint8_t reg, uint8_t* data, uint16_t length);

uint8_t nrf24l01_write_register(nrf24l01_device * device, uint8_t reg, uint8_t* data, uint16_t length);
 // End of NRF24L01_REGISTER_ACCESS group


uint8_t nrf24l01_read_rx_payload(nrf24l01_device * device, uint8_t* data, uint16_t length);

uint8_t nrf24l01_write_tx_payload(nrf24l01_device * device, uint8_t* data , uint16_t length);

uint8_t nrf24l01_write_ack_payload(nrf24l01_device * device, uint8_t* data, uint8_t pipe, uint16_t length);

uint8_t nrf24l01_write_tx_payload_no_ack(nrf24l01_device * device, uint8_t * data, uint16_t length);

uint8_t nrf24l01_read_rx_payload_width(nrf24l01_device * device, uint8_t* data);
 // End of NRF24L01_PAYLOAD_ACCESS group


uint8_t nrf24l01_flush_tx(nrf24l01_device * device);

uint8_t nrf24l01_flush_rx(nrf24l01_device * device);

uint8_t nrf24l01_reuse_tx_payload(nrf24l01_device * device);
 // End of NRF24L01_FIFO_CONTROL group


uint8_t nrf24l01_activate_extra_features(nrf24l01_device * device);

uint8_t nrf24l01_nop(nrf24l01_device * device);
 // End of NRF24L01_ADVANCED_FEATURES group


uint8_t nrf24l01_power_up(nrf24l01_device * device);

uint8_t nrf24l01_power_down(nrf24l01_device * device);
 // End of NRF24L01_POWER_CONTROL group


uint8_t nrf24l01_transmit(nrf24l01_device * device);

uint8_t nrf24l01_listen(nrf24l01_device * device);
 // End of NRF24L01_MODE_CONTROL group


uint8_t nrf24l01_dynamic_payload_length(nrf24l01_device * device, uint8_t enable);

uint8_t nrf24l01_payload_with_ack(nrf24l01_device * device, uint8_t enable);

uint8_t nrf24l01_dynamic_ack(nrf24l01_device * device, uint8_t enable);
 // End of NRF24L01_FEATURE_CONTROL group


uint8_t nrf24l01_data_pipe_dynamic_payload_length(nrf24l01_device * device, uint8_t pipe_number, uint8_t enable);

uint8_t nrf24l01_data_pipe_enable(nrf24l01_device * device, uint8_t pipe_number, uint8_t enable);

uint8_t nrf24l01_data_pipe_auto_ack(nrf24l01_device * device, uint8_t pipe_number, uint8_t enable);

uint8_t nrf24l01_data_pipe_address(nrf24l01_device * device, uint8_t pipe_number, uint8_t * address, uint8_t length);

uint8_t nrf24l01_data_pipe_payload_width(nrf24l01_device * device, uint8_t pipe_number, uint8_t width);
 // End of NRF24L01_PIPE_CONTROL group


uint8_t nrf24l01_interrupt(nrf24l01_device * device, nrf24l01_irq irq, uint8_t enable);

uint8_t nrf24l01_clear_interrupt_flag(nrf24l01_device * device, nrf24l01_irq irq);
 // End of NRF24L01_INTERRUPT_CONTROL group
 // End of NRF24L01_FUNCTIONS group
 
#endif //NRF24L01_DRIVER_NRF24L01_H